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Lozada Padilla DP, Zamora Pérez CD, Rodriguez Garcia RM, Ortega Méndez G, Mejía Salvador JS, Montiel Hernández JF. A Traceable Design Flow for Synchronous FPGA Architectures From State Machine Specification to Hardware Validation on the Alhambra II Platform. Int. Journal of COP and Infor. [Internet]. 2026 Sep. 21 [cited 2026 Sep. 21];18(1):111-25. Available from: https://ijcopi.org/ojs/article/view/1508