[1]
D. P. Lozada Padilla, C. D. Zamora Pérez, R. M. Rodriguez Garcia, G. Ortega Méndez, J. S. Mejía Salvador, and J. F. Montiel Hernández, “A Traceable Design Flow for Synchronous FPGA Architectures From State Machine Specification to Hardware Validation on the Alhambra II Platform”, Int. Journal of COP and Infor., vol. 18, no. 1, pp. 111–125, Sep. 2026.